[DynInst_API:] [dyninst/dyninst] e0b477: 10/23

[Yuhan Xie]

Branch: refs/heads/power_vector
Home: https://github.com/dyninst/dyninst
Commit: e0b47787f00797171ceded23427c0b4abd25dfcc
https://github.com/dyninst/dyninst/commit/e0b47787f00797171ceded23427c0b4abd25dfcc
Author: Yuhan Xie <***@wisc.edu>
Date: 2018-10-23 (Tue, 23 Oct 2018)

Changed paths:
M common/h/entryIDs.h
M instructionAPI/src/power_opcode_tables.C

Log Message:
-----------
10/23
Chapter 6

new:
keyword CY, 21th bit
keyword ST, 16th bit
keyword SIX, 17-20
keyword DRM, 18-20
keyword RM, 19-20
(ST and SIX always show up together)
keyword PS, 22th bit

Summary of Changable fields:
UIM:
11-15:
4-906 vctuxs,
4-970 vctsxs,

12-15:
4-524 vspltb
4-525 vextractub
4-589 vextractuh
4-653 vextractuw
4-717 vextractd
4-781 vinsertb
4-845 vinserth
4-909 vinsertw
4-973 vinsertd

4-588 vsplth 13-15

4-652 vspltw 14-15

Rc bit:
for opcode 4: always 21th bit

6-bit(26-31) ext opcode for opcode 4:
32-47, 59-63



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